Back to library

🧵Understand Concurrency Memory Models and Write Race-Free Code

Stop guessing whether your atomics need `seq_cst` and start picking orderings from first principles — one primitive at a time — until you can write a lock-free counter that provably can't race.

Advanced14 drops~2-week path · 5–8 min/daytechnology

Phase 1Why Memory Models Exist

See why sequential consistency is a lie you rely on

4 drops
  1. Your program runs in an order nobody wrote

    7 min

    Your program runs in an order nobody wrote

  2. A data race and a race condition are not the same bug

    6 min

    A data race and a race condition are not the same bug

  3. Five memory orderings, each with a different job

    7 min

    Five memory orderings, each with a different job

  4. Store buffers are why your store didn't show up yet

    7 min

    Store buffers are why your store didn't show up yet

Phase 2Happens-Before on Paper

Reason about happens-before with tiny, concrete programs

5 drops
  1. Happens-before is a graph, not a clock

    8 min

    Happens-before is a graph, not a clock

  2. Release is how you hand data to another thread

    7 min

    Release is how you hand data to another thread

  3. Acquire is how you claim what was published

    7 min

    Acquire is how you claim what was published

  4. CAS isn't just an atomic swap — it's an ordering decision

    8 min

    CAS isn't just an atomic swap — it's an ordering decision

  5. Relaxed is correct exactly when you don't care about order

    7 min

    Relaxed is correct exactly when you don't care about order

Phase 3Picking the Right Ordering

Compare seq_cst, acquire/release, and relaxed in real patterns

4 drops
  1. You inherit a spinlock that deadlocks only on ARM

    8 min

    You inherit a spinlock that deadlocks only on ARM

  2. The reference count that crashes during destruction

    8 min

    The reference count that crashes during destruction

  3. The once-init that double-runs on two cores

    8 min

    The once-init that double-runs on two cores

  4. The SPSC queue that drops messages under load

    8 min

    The SPSC queue that drops messages under load

Phase 4Build a Lock-Free Counter

Write and defend a correct lock-free counter

1 drop
  1. Ship a lock-free counter you can defend

    8 min

    Ship a lock-free counter you can defend

Frequently asked questions

What is a data race, and is it different from a race condition?
This is covered in the “Understand Concurrency Memory Models and Write Race-Free Code” learning path. Start with daily 5-minute micro-lessons that build from fundamentals to hands-on application.
When is it safe to use memory_order_relaxed?
This is covered in the “Understand Concurrency Memory Models and Write Race-Free Code” learning path. Start with daily 5-minute micro-lessons that build from fundamentals to hands-on application.
What does happens-before actually mean?
This is covered in the “Understand Concurrency Memory Models and Write Race-Free Code” learning path. Start with daily 5-minute micro-lessons that build from fundamentals to hands-on application.
Why isn't volatile enough for thread safety?
This is covered in the “Understand Concurrency Memory Models and Write Race-Free Code” learning path. Start with daily 5-minute micro-lessons that build from fundamentals to hands-on application.
Do I need seq_cst for a counter?
This is covered in the “Understand Concurrency Memory Models and Write Race-Free Code” learning path. Start with daily 5-minute micro-lessons that build from fundamentals to hands-on application.